A commonly-used processor is formed of a single LSI of a chip and a package or is formed of a plurality of LSIs. When a failure occurs in an LSI of the processor, such a faulty LSI is discarded for replacement with a good one while the remaining operable LSIs are used intact.
Recent semiconductor technology has dramatically improved the scale of processor implementable by a single chip. For example, the world's first microprocessor, introduced in 1971, is a 4-bit processor. At ISSCC held in 1992, a microprocessor, in which two 32-bit CPUs and cache are concentrated in a single chip by 0.3 .mu.m BiCMOS technology, was reported. Also, in the field of parallel computing, a processor was reported in 1994 at ISSCC, in which 0.55 .mu.m BiCMOS technology is used to integrate 64 8-bit element processors in a single chip.
According to the classification of processors by Flynn, they are classified into four types depending on the respective numbers of instructions and data items to be dealt with, namely (1) SISD (Single Instruction Single Data stream), (2), SIMD (Single Instruction Multi Data stream), (3) MISD and (4) MIMD. The former microprocessor is classified as an MIMD processor and the latter processor is classified as an SIMD processor. The very long instruction word (VLIW) instruction processor, which uses a VLIW instruction composed of a great number of instructions, may be classified as follows. A VLIW instruction processor is classified as an SIMD processor when a VLIW instruction is taken as a single instruction, while on the other hand it is classified as an MIMD processor when it is considered such that the operations of individual execution units are instructed by individual instructions contained in a VLIW instruction.
In any case of employing any one of MIMD, SIMD and VLIW as a processor, it is estimated that a great number of processors (execution units) are mounted on a single chip, for the semiconductor technology generation changes every three years and it is expected that such a change in the semiconductor technology generation will continue until the year of 2010.
However, integration of a great number of execution units in a single chip produces some problems. One of the problems is that the cost of chips increases if a defect in a single execution unit results in discarding an entire chip containing also normally operable execution units.
Major elements of a processor are an instruction control unit, an execution unit, a register file, an instruction cache, a data cache, a memory management unit, a bus control unit and a main memory. It is expected that main memory is incorporated in the same chip in the near future. For the case of storage elements requiring larger areas in the chip such as register file, instruction cache, data cache and main memory, redundant parts which function in case they fail to operate normally are provided, as in DRAMs. In other words, a faulty part is replaced with a corresponding redundant part, so that the above-described problem can be solved. On the other hand, elements, such as instruction control units, memory management units and bus control units, require less chip area, so that the rate of failure occurrence is low. Difficulties occur when greater area requiring elements other than storage elements, i.e., execution units and element processors in the case of parallel computing, fail to normally operate.
Various measurements have been proposed to cope with such an execution unit failure problem. Japanese Patent Application Laid Open Gazette No. 5-216852 discloses a technique. A data processor with first and second instruciton execution control units is shown which has the ability to perform instructions in parallel. When "collision" of instructions occurs, that is, when they cannot be executed at the same time, (a) these instructions are executed in one of the two instruction execution control units (for example, the first instruction execution control unit), (b) the second instruction execution control unit also executes the instructions that the first instruction execution control unit is executing and (c) results of the first and second units are compared in a failure detection circuit, to detect an instruction execution control unit failure. When such a failure is detected in one of the instruction execution control units, only the other instruction execution control unit which is a normally operable unit is used to execute the instructions on series.
Japanese Patent Application Laid Open Gazette No. 5-216852, however, produces an inconvenient circumstance that the detecting of a failure can be made only when any one of the instruction execution control units is not in use or operation, in other words failures cannot be detected when a plurality of instructions are being performed in parallel in both the instruction execution control units. This means that, even when any one of the instruction execution control units fails at the time when parallel instruction processing is being executed, it is necessary to wait for one of the instruction execution control units to enter the idle state, to start detecting the failure. Accordingly, many instructions will have been executed by the time that the failure is detected. To sum up, the above-described prior art technology is unable to find failures in early stages and lacks the ability to secure normal operations for processors. Although, in general, the presence or absence of an initial failure in each instruction execution control unit may be detected by failure detection testing made immediately after their fabrication (hereinafter referred to post-fabrication failure detection testing), the prior art technique shown in the foregoing gazette is not provided with a means capable of reporting, when an initial failure is detected in post-fabrication failure detection testing, such an initial failure, as a result of which, when a data processor starts operating without being discarded, it is not until a failure detection circuit discovers the failure during the data processor's operation that a faulty instruction execution unit is screened out. Accordingly, in the prior art technique, failures cannot be detected in early stages and processor's normal operations cannot be secured, either.